Read the original article here.

---

Understanding CPLDs: A Resource for Building a Computer from Scratch

In the journey of building a computer from its fundamental components, understanding various types of integrated circuits is essential. While microprocessors and memory chips are central, custom logic is often needed to connect, control, and coordinate these components. This is where programmable logic devices come into play. This resource delves into Complex Programmable Logic Devices (CPLDs), explaining what they are, how they work, and their potential role in a custom computer build.

1. What is a CPLD?

A Complex Programmable Logic Device (CPLD) is a type of digital integrated circuit that allows designers to implement custom logic functions. Unlike standard "fixed-function" chips like logic gates (AND, OR, NOT), multiplexers, or decoders, the internal logic of a CPLD is programmable after the chip is manufactured.

Think of it as a versatile chip that can be configured to perform a wide range of logical tasks, replacing numerous smaller, fixed-function chips. This flexibility makes them invaluable in custom hardware design, including the kind of bespoke logic often required when building a computer system from scratch.

Integrated Circuit (IC) Also known as a chip or microchip, an integrated circuit is a set of electronic circuits on one small flat piece of semiconductor material, usually silicon. Different components like transistors, resistors, and capacitors are miniaturized and combined on a single chip to perform specific functions.

Programmable Logic Refers to digital logic circuits whose function is not fixed during manufacturing but can be configured or programmed by the user after the device is made. This allows for flexible design implementation and modification.

2. Historical Context: The Evolution of Programmable Logic

CPLDs didn't appear out of nowhere. They are the evolution of simpler programmable logic devices (PLDs) developed in the 1970s and 80s to overcome the limitations of using only fixed-function Small-Scale Integration (SSI) and Medium-Scale Integration (MSI) chips (like standard logic gates, flip-flops, decoders, etc.).

• Programmable Logic Arrays (PLAs): These were early devices with programmable AND gates feeding into programmable OR gates. This architecture offered high flexibility but could be slow due to the programmable nature of both planes.

  AND Plane / OR Plane In programmable logic, these refer to arrays of logic gates. An AND plane typically takes input signals and their complements and allows creating product terms (AND combinations). An OR plane then takes these product terms and allows creating sum-of-products expressions (OR combinations of the product terms). The "programmable" aspect means you can connect or disconnect inputs to the gates within these planes.

• Programmable Array Logic (PALs): An improvement over PLAs, PALs simplified the structure by having a programmable AND plane feeding into a fixed OR plane. This made them faster and simpler to manufacture and program than PLAs.

  PAL (Programmable Array Logic) A programmable logic device with a programmable AND array and a fixed OR array.

• Generic Array Logic (GALs): These were electrically erasable and reprogrammable versions of PALs, often featuring a configurable output structure (allowing registered or combinatorial output). This added significant flexibility as design changes could be made without discarding chips.

  GAL (Generic Array Logic) A PAL with reprogrammable (typically EEPROM or Flash) configuration and configurable outputs, often implemented using a macrocell structure.

CPLDs emerged as the next step, offering more logic capacity and improved interconnectivity compared to their PAL/GAL predecessors. They were designed to handle more complex tasks and integrate the functionality of many PALs/GALs onto a single chip.

3. CPLD Architecture: Building Blocks

Understanding how a CPLD works requires looking at its internal structure. CPLDs typically consist of several key components:

• Input/Output Blocks (IOBs): These are the interfaces between the CPLD's internal logic and the outside world (the pins of the chip). IOBs can often be configured to handle different electrical standards, drive strengths, or include pull-up/pull-down resistors. They manage the signals going into and out of the device.

• Logic Array Blocks (LABs) or Function Blocks (FBs): These are the core processing units within a CPLD. Each LAB contains a collection of programmable logic resources, most notably:

  • Macrocells: This is the fundamental unit within a LAB. A macrocell typically contains programmable logic (often an AND-OR array similar to a PAL/GAL) to implement combinatorial functions, and one or more registers (flip-flops) for implementing sequential logic. The output of the logic array can be routed directly to the output or stored in a register.
  • Internal Routing Pool: Within a LAB, there's local routing that allows macrocells to connect to each other.

• Programmable Interconnect Array (PIA): This is the network that connects the different LABs, IOBs, and other resources within the C CPLD. Unlike the fine-grained, highly flexible (and sometimes unpredictable) routing in FPGAs, the interconnect in a CPLD is generally more structured and block-oriented, contributing to its predictable delay characteristics.

Macrocell A fundamental building block in a CPLD, typically containing programmable logic (like an AND-OR array) and one or more registers (flip-flops). It can implement both combinatorial and sequential logic functions.

Register / Flip-Flop A basic memory element in digital circuits that can store a single bit of information. Flip-flops are used to create sequential logic, allowing circuits to have memory and perform operations based on past inputs or states.

4. How CPLDs Work

At its core, a CPLD implements digital logic functions by configuring its internal programmable switches.

1. Design Input: The desired logic function (e.g., "output C is high if input A is high AND input B is low") is described by the designer using design entry methods. These can range from schematic capture (drawing diagrams with logic gates) to Hardware Description Languages (HDLs) like VHDL or Verilog.

   Hardware Description Language (HDL) A specialized computer language used to describe the structure and behavior of electronic circuits, such as digital logic circuits. VHDL and Verilog are common examples.

   Schematic Capture A design entry method where circuits are represented visually using standard symbols for logic gates, flip-flops, and other components, and drawing wires to connect them.

2. Synthesis and Place & Route: Software tools take the design description (HDL or schematic) and translate it into a configuration pattern specific to the target CPLD device. This process involves:

   • Synthesis: Translating the high-level design description into a netlist of generic logic gates and flip-flops.
   • Mapping/Packing: Fitting these logic elements into the specific resources available in the CPLD's LABs/macrocells.
   • Place and Route: Deciding which specific macrocells/LABs will implement which part of the design ("place") and determining the paths through the programmable interconnect ("route") to connect them correctly.

3. Configuration/Programming: The generated configuration pattern is loaded into the CPLD's non-volatile memory cells (typically EEPROM, Flash, or similar). These memory cells control the programmable switches within the device, effectively wiring up the internal logic gates and connections according to the designer's specification.

4. Operation: Once programmed, the CPLD behaves as the custom digital circuit defined by the configuration, performing the specified logic functions on its inputs to produce the required outputs.

The use of an AND-OR array structure within macrocells is common. Inputs to the macrocell feed into the programmable AND array, generating various "product terms" (ANDed combinations of inputs). These product terms then feed into the programmable OR array (or a fixed OR gate in some simpler structures) to create "sum-of-products" logic expressions. The output of this logic can then pass through a register (flip-flop) if sequential behavior is needed.

5. CPLDs vs. FPGAs: Key Differences

CPLDs are often compared to Field-Programmable Gate Arrays (FPGAs). While both are types of programmable logic devices, they have significant architectural and characteristic differences that make them suitable for different tasks:

• Architecture:

  • CPLD: Characterized by relatively large blocks of logic (LABs/macrocells) interconnected by a programmable fabric. The interconnect is structured and more predictable.
  • FPGA: Characterized by a fine-grained array of small, simple logic cells (often based on Look-Up Tables or LUTs) distributed across the chip, surrounded by a more complex, flexible, and dense programmable routing fabric.

    FPGA (Field-Programmable Gate Array) A programmable logic device characterized by a large array of simple, identical logic cells, a flexible interconnect fabric, and surrounding I/O blocks. FPGAs offer much higher capacity and flexibility than CPLDs but often have less predictable timing.

    Look-Up Table (LUT) A fundamental logic element in many FPGAs. A LUT is essentially a small memory that stores the output value for every possible combination of its inputs. This allows it to implement any boolean function of its inputs.

• Configuration Memory:

  • CPLD: Most CPLDs use non-volatile memory technologies like EEPROM or Flash to store their configuration. This means they retain their programming even when power is removed and are instantly configured upon power-up.
  • FPGA: Most FPGAs use SRAM (Static Random-Access Memory) for configuration. SRAM is volatile, so the FPGA loses its configuration when power is removed. FPGAs thus require an external configuration source (like a serial Flash chip or a microcontroller) to load their program every time the system starts up.

    Non-Volatile Memory Memory that retains its data even when the power supply is removed (e.g., Flash memory, EEPROM).

    SRAM (Static Random-Access Memory) A type of volatile memory that retains its data as long as power is supplied. Widely used in FPGAs for configuration and high-speed caches/memory within the device.

• Timing Predictability:

  • CPLD: Due to their more structured, block-oriented architecture and less complex interconnect, CPLDs generally have more predictable and often faster pin-to-pin delays for combinatorial logic.
  • FPGA: The highly flexible, fine-grained routing in FPGAs can lead to more variability in delays depending on how the design is placed and routed. Achieving timing closure (meeting timing requirements) can be more complex in FPGAs, especially for high-speed designs.

• Size and Complexity:

  • CPLD: Typically offer logic capacities ranging from tens to a few thousand macrocells, suitable for implementing several hundred to a few thousand equivalent logic gates.
  • FPGA: Can contain tens of thousands to millions of logic cells (LUTs) and dedicated blocks (DSP slices, memory blocks, even processors), supporting designs with millions of equivalent logic gates. FPGAs are much larger and more complex devices capable of implementing entire systems.

6. Advantages of CPLDs

• Non-Volatile Configuration: They power up instantly configured, without needing an external configuration device or boot-up time. This is critical for tasks required immediately upon system power-on (like bus control or initial address decoding).
• Predictable Timing: Their architecture leads to relatively predictable signal delays, simplifying timing analysis for critical control paths.
• Lower Cost: For simpler tasks, a CPLD is often significantly cheaper than an equivalent FPGA.
• Lower Power (for simple designs): For small to medium logic implementations, CPLDs can consume less power than FPGAs.
• Easier to Use (for simple designs): The development tools and design flow can sometimes be simpler for CPLDs than for complex FPGAs.

7. Limitations of CPLDs

• Limited Logic Capacity: They cannot implement large, complex digital systems like modern FPGAs can. You cannot build a sophisticated CPU or a video controller with a CPLD.
• Limited Dedicated Resources: Unlike FPGAs, CPLDs typically lack dedicated blocks for tasks like high-speed memory interfaces, DSP (Digital Signal Processing), or embedded processors.
• Less Flexible Routing: While predictable, the interconnect structure is less flexible than the fine-grained routing in FPGAs, which can sometimes make achieving optimal resource utilization more challenging for complex logic within a single LAB.

8. Applications in "Building a Computer from Scratch"

Given their characteristics, CPLDs are well-suited for specific "glue logic" and control tasks in a custom computer build. They excel at consolidating the functionality of many smaller chips into one, saving board space, power, and complexity. Here are some common use cases:

• Address Decoding: This is perhaps one of the most common and crucial roles. A CPLD can take address lines from the CPU and generate chip select signals for different memory chips (RAM, ROM, peripherals) based on defined address ranges. This replaces multiple discrete decoder chips (like 74LS138s).

  • Example: Program the CPLD to assert /CS_RAM when the address is between $0000-$7FFF, /CS_ROM when between $8000-$FFFF, and /CS_IO for a specific upper address range.

• Control Signal Generation: Generating appropriate read/write strobes, interrupt request/acknowledge signals, wait states, or other control signals based on the CPU's status lines and the current address.

  • Example: Combine the CPU's /MREQ (Memory Request) and /RD (Read) signals with the decoded /CS_ROM signal to generate a buffered /ROM_OE (Output Enable) signal with specific timing.

• Bus Interface Logic: Implementing logic to buffer signals, manage direction control for bidirectional buses, or adapt timing between different components on the bus.

• Simple State Machines: Controlling simple sequential processes, such as managing the timing of a peripheral device or sequencing specific operations during system startup or reset.

• Consolidating Glue Logic: Replacing numerous general-purpose logic gates, multiplexers, demultiplexers, and simple registers required to interface different components. This significantly cleans up the circuit board and reduces wiring complexity.

• Reset and Clock Generation/Management: Generating or conditioning reset signals, or creating simple clock dividers or enable signals.

• Boot-up Logic: Because of their non-volatility and instant-on nature, CPLDs are ideal for the logic needed immediately when the system powers up, before a volatile device like an FPGA or even the CPU can begin execution (which might require the CPLD to enable the boot ROM first!).

In essence, a CPLD can serve as the central nervous system for the passive components and control signals in your custom computer, handling the critical initial setup and ongoing coordination that the CPU itself might not be designed to do directly or efficiently using discrete logic.

9. Programming and Tools

Configuring a CPLD requires specific hardware and software:

• Design Tools: Software from the CPLD manufacturer (like Xilinx ISE/Vivado for older/newer devices, or Altera/Intel Quartus) is used for design entry (HDL or schematic), synthesis, place & route, and generating the programming file.
• Programming Hardware: A programming cable/pod is needed to connect the computer running the design software to the target CPLD on your circuit board.
• Programming Interface: CPLDs are typically programmed via a JTAG (Joint Test Action Group) interface or a manufacturer-specific In-System Programming (ISP) method. This allows you to program the chip while it's soldered onto your board.

  JTAG (Joint Test Action Group) An industry standard for verifying designs and testing printed circuit boards after manufacture. It provides a standard interface (often 4 or 5 pins) for debugging and in-system programming of compatible devices like CPLDs and FPGAs.

  In-System Programming (ISP) The ability to program a device (like a CPLD or microcontroller) while it is already soldered onto a circuit board, without needing to remove it.

The process involves writing code or drawing schematics describing the desired logic, compiling it using the manufacturer's software, and then using the programming hardware to load the resulting configuration file onto the CPLD via its programming interface.

10. Summary

Complex Programmable Logic Devices (CPLDs) represent a crucial step in the evolution of digital design, bridging the gap between simple PALs/GALs and complex FPGAs. Their block-based architecture, non-volatile configuration, and predictable timing make them excellent choices for implementing moderate-sized logic functions, consolidating "glue logic," and handling critical, instant-on tasks like address decoding and control signal generation.

For hobbyists and engineers embarking on projects like "Building a Computer from Scratch," CPLDs offer a powerful and flexible way to replace dozens of smaller, fixed-function integrated circuits with a single, programmable chip. This not only simplifies the board layout and reduces component count but also allows for easy modification and iteration of the control logic as the design evolves. Understanding CPLDs is a valuable skill in the art of crafting custom digital hardware.