Read the original article here.

---

Understanding Field-Programmable Gate Arrays (FPGAs) for Building Digital Hardware

In the journey of understanding how computers are built, we start with fundamental building blocks: logic gates, flip-flops, registers, and combinational/sequential circuits. Traditionally, experimenting with complex digital designs involved physically wiring components on breadboards or designing custom Integrated Circuits (ICs), which is expensive and time-consuming. This is where Field-Programmable Gate Arrays (FPGAs) become an incredibly powerful tool.

FPGAs allow you to design and implement complex digital circuits without the need for physical fabrication for each new design. They provide a reconfigurable platform that bridges the gap between theoretical digital logic design and practical hardware implementation.

What is an FPGA?

A Field-Programmable Gate Array (FPGA) is a type of integrated circuit (IC) that can be configured or reprogrammed after manufacturing. Unlike fixed-function chips like microprocessors or memory, an FPGA contains a large array of uncommitted digital logic that can be interconnected in virtually any way the designer specifies.

Think of an FPGA as a vast, reconfigurable electronic breadboard filled with fundamental digital components (like logic gates, memory elements, and wiring channels) that you can connect and configure using software. The term "Field-Programmable" means you can program it outside the factory, right there "in the field" (your lab, your desk, etc.).

FPGAs are a subset of Programmable Logic Devices (PLDs), which are ICs designed to be configurable. Older PLDs like Programmable Array Logic (PALs) or Generic Array Logic (GALs) offered limited configuration, typically focused on sum-of-products logic. FPGAs, however, offer a much higher degree of flexibility and capacity.

Why Use FPGAs When Learning to Build a Computer?

When you're learning to build a computer from scratch, an FPGA is your digital playground.

• Rapid Prototyping: Instead of building a CPU circuit with discrete chips or waiting months for a custom chip design, you can describe your CPU's logic in software and upload it to the FPGA in minutes. You can then test it, find errors, modify the design, and reprogram the FPGA instantly.
• Hardware Experimentation: You can experiment with different architectures, build custom peripherals (like video controllers or specific interfaces), and truly see your digital logic designs come to life and interact with the real world.
• Learning Hardware Design: FPGAs require you to think in terms of parallel hardware execution, which is fundamentally different from sequential software programming. This perspective is crucial for understanding how real hardware works.

A Brief History of FPGAs

The concept of programmable logic evolved from earlier technologies like Programmable Read-Only Memory (PROM) and simpler PLDs. These early devices allowed some level of customization after manufacturing.

• In 1983, Altera was founded, introducing their first reprogrammable device, the EP300, in 1984. This chip used EPROM technology, which could be erased with UV light through a quartz window on the package – a primitive form of reconfigurability.
• A major breakthrough came in 1985 when Xilinx produced the first commercially viable FPGA, the XC2064. This chip had the key features: programmable logic blocks (they called them Configurable Logic Blocks, or CLBs) and programmable interconnects between them. The XC2064 was quite simple by today's standards, with only 64 CLBs, each containing rudimentary logic like 3-input lookup tables (LUTs).
• The 1990s saw rapid advancement in FPGA density and sophistication. They moved from simple "glue logic" (connecting other chips on a board) to implementing significant portions of system functionality.
• Initially, FPGAs were primarily used in specialized fields like telecommunications and networking where flexibility and speed were critical and production volumes were low.
• Over time, their increasing capacity and decreasing relative cost allowed them to penetrate wider markets, including consumer electronics, automotive, and industrial applications.
• Today, major tech companies like Microsoft (Bing search engine, Azure cloud) use FPGAs for accelerating computationally intensive tasks due to their performance-per-watt efficiency and ability to execute highly parallel algorithms directly in hardware.

The growth trajectory reflects the increasing complexity and capacity of these chips: from thousands of "gates" (a rough measure of logic capacity) in the late 1980s to tens of millions in the 2010s.

The Anatomy of an FPGA: Core Components

Understanding how an FPGA works internally is key to utilizing it effectively. While architectures vary between manufacturers, the core components are broadly similar:

1. Configurable Logic Blocks (CLBs) / Logic Array Blocks (LABs): These are the fundamental computational units of the FPGA. They are arranged in a grid or array. Each block contains the basic elements needed to implement combinational and sequential logic.

   • Details: A typical CLB often contains:
     • Lookup Tables (LUTs): These are the heart of combinational logic within a CLB. A LUT is essentially a small memory (SRAM) used to implement a truth table. A K-input LUT can implement any boolean function of K inputs. A 4-input LUT (common in older FPGAs) can implement any function of 4 inputs. By storing the output of the truth table for all possible input combinations, the LUT can act as a custom logic gate.
       • Example: A 2-input LUT can implement AND, OR, XOR, NAND, NOR, XNOR, or any other function of two inputs by loading the appropriate 4-bit value into its internal SRAM.
     • Flip-Flops (usually D-type): These provide the sequential logic capability, allowing the circuit to store state over time. The output of the combinational logic (from the LUTs) can be fed into a flip-flop to create registers or state machines.
     • Multiplexers (Muxes): These are used within the CLB to select different data paths, for instance, choosing whether the output of the LUT directly feeds an output pin or goes through a flip-flop first (synchronous vs. asynchronous output).
     • Carry Logic (Fast Adders): Many CLBs include dedicated hardware to accelerate arithmetic operations like addition, which would otherwise require chaining multiple LUTs and could be slow.

2. Programmable Interconnect: This is the network of wires and programmable switches that connects the outputs of CLBs, I/O pads, and other resources to the inputs of other components.

   • Details: This interconnect network is highly flexible. The "programming" of the FPGA primarily involves configuring these switches to create the desired connections between logic blocks. The complexity of routing (finding paths for all the necessary connections) is often the limiting factor in fitting a large design onto an FPGA. Manufacturers design the routing network with various lengths and speeds of wires to accommodate different timing requirements.

3. Input/Output (I/O) Pads: These are the connections that allow the FPGA to interface with external components on a circuit board.

   • Details: I/O pads can be configured for various voltage standards and signaling types. Many have programmable features like slew rate control (controlling how fast the output signal transitions, useful for reducing noise) and built-in termination resistors. Higher-end FPGAs feature very high-speed I/O blocks used for modern digital interfaces.

Extending Functionality: Hard and Soft Blocks

As FPGAs grew, designers realized that implementing common, complex functions (like arithmetic multipliers, large blocks of memory, or even processor cores) purely out of CLBs and interconnect was inefficient in terms of area, speed, and power. This led to the inclusion of dedicated, pre-designed hardware blocks, sometimes called "hard blocks" or "hard IP."

• Hard Blocks: These are sections of the silicon chip dedicated to a specific function, built using standard ASIC-like design techniques. Because they are fixed, they are much more efficient than building the same function from the general programmable fabric.

  • Examples:
    • DSP Blocks: Optimized for digital signal processing tasks (multiplication, accumulation). Crucial for audio, video, and communications processing.
    • Embedded Memory Blocks (Block RAM): Dedicated blocks of SRAM providing denser, faster memory than implementing memory using distributed LUTs and flip-flops. Useful for data buffers, lookup tables, or even small data/instruction memories for embedded processors.
    • High-Speed Transceivers (SERDES): Handle very fast serial communication (like PCIe, Ethernet, USB 3.0+). These often include analog components that cannot be implemented in the digital logic fabric.
    • Processor Cores: Some high-end FPGAs include one or more complete CPU cores (often ARM processors) built into the silicon. This creates a powerful System on a Programmable Chip (SoPC) or System on a Chip (SoC), allowing a blend of fixed CPU performance and custom programmable logic for acceleration or peripherals.

• Soft Cores: In contrast to hard blocks, a "soft core" is a processor or other complex peripheral design that is implemented entirely using the FPGA's programmable logic fabric (CLBs, interconnect, Block RAM).

  • Examples: The Xilinx MicroBlaze or Altera (Intel) Nios II are popular examples of softcore processors.
  • Pros: Highly customizable – you can tailor the processor's instruction set or add/remove features based on your needs. Uses only the standard fabric resources.
  • Cons: Typically slower, consume more power, and use significantly more FPGA logic resources than an equivalent hard processor core.

Choosing between implementing a function with a soft core (if available/suitable) or utilizing a hard block (if the FPGA has one) is a key design decision depending on performance requirements, resource availability, and flexibility needs.

Clocking and Timing in FPGAs

Digital circuits, especially synchronous ones, rely heavily on a clock signal to coordinate operations. Timing is absolutely critical in FPGA design, perhaps even more so than in ASIC design due to the complexities of the programmable interconnect.

• Clock Networks: FPGAs have dedicated, low-skew routing networks specifically for distributing clock signals across the chip. These are often organized in structures like an "H-tree" to ensure the clock arrives at flip-flops and other sequential elements at roughly the same time, minimizing "clock skew."
• Clock Management Tiles: FPGAs include specialized blocks containing Phase-Locked Loops (PLLs) or Delay-Locked Loops (DLLs). These blocks can take an input clock frequency (e.g., from an external oscillator) and generate multiple output clocks with different frequencies, phases, and duty cycles. This is essential for generating the various clock signals needed by complex systems and managing clock jitter.
• Clock Domains: Large designs often use multiple clocks running at different frequencies or phases. Each distinct clock signal defines a "clock domain."
• Clock Domain Crossing (CDC): Transferring data reliably between circuits operating in different clock domains is a significant challenge in digital design. Special synchronization circuits are required to avoid metastability, a state where a flip-flop's output is neither a solid '0' nor a solid '1', potentially leading to system failure. FPGAs often provide features like dual-port RAM blocks specifically designed to allow reads and writes from different clock domains, facilitating the creation of FIFOs (First-In, First-Out buffers), a common CDC technique.

Setup and Hold Times: These are fundamental timing requirements for synchronous elements like flip-flops.

• Setup Time: The data input to a flip-flop must be stable for a minimum amount of time before the active clock edge arrives.
• Hold Time: The data input must remain stable for a minimum amount of time after the active clock edge arrives. If these requirements are not met due to signal propagation delays through the logic and interconnect, the flip-flop may go metastable, leading to unpredictable results. FPGA design tools perform extensive timing analysis to ensure setup and hold times are met across the entire design, considering the delays introduced by the specific placement and routing.

The Design Flow: Programming an FPGA

Programming an FPGA isn't like writing software for a CPU. Instead of compiling sequential instructions, you are defining a hardware circuit using specialized tools and languages.

1. Design Entry:

   • Hardware Description Languages (HDLs): The most common way to design for FPGAs. You write code that describes the structure and behavior of your digital circuit.
     • VHDL (VHSIC Hardware Description Language): A strongly-typed, somewhat verbose HDL, often used in defense and aerospace.
     • Verilog: A more C-like syntax, widely used in commercial design.
   • Schematic Entry: For smaller designs or specific modules, you can sometimes draw the circuit using graphical symbols for gates, flip-flops, etc. This visually represents the circuit structure.
   • High-Level Synthesis (HLS): Newer approaches allow you to describe complex algorithms in higher-level languages like C, C++, or OpenCL. An HLS tool then attempts to automatically generate an HDL description of the hardware circuit needed to perform that algorithm.

2. Synthesis: An Electronic Design Automation (EDA) tool takes your HDL description and translates it into a "netlist."

   A Netlist is a description of the circuit in terms of basic logical elements (like AND gates, OR gates, flip-flops) and how they are connected. It's an intermediate representation of your design before it's mapped to a specific target technology (like an FPGA).

3. Technology Mapping: The tool maps the elements in your generic netlist to the specific resources available in the target FPGA device (e.g., mapping basic logic to LUTs, registers to flip-flops within CLBs, arithmetic to dedicated adders or DSP blocks).

4. Place and Route: This is where the design is physically laid out on the FPGA.

   • Placement: The tool decides which specific CLB, Block RAM, DSP block, etc., on the FPGA grid will implement each part of your mapped design.
   • Routing: The tool determines the paths through the programmable interconnect to connect all the placed components according to the netlist. This is a complex optimization problem, trying to meet timing requirements while using available routing resources.

5. Timing Analysis: After place and route, the tool knows the exact physical paths and thus the signal propagation delays. It performs a static timing analysis to verify that the circuit will operate correctly at the specified clock frequency, ensuring all setup and hold times are met. If timing is not met, the designer must go back, modify the design or constraints, and repeat the flow.

6. Bitstream Generation: If timing and other checks pass, the tool generates a Bitstream.

   A Bitstream is a binary file containing the configuration data specific to the target FPGA device. This data tells the FPGA how to set up its internal LUTs, configure its flip-flops, and program its interconnect switches to implement your designed circuit.

7. Device Configuration: The bitstream is loaded onto the FPGA.

   • For most modern SRAM-based FPGAs, the bitstream is typically stored in an external non-volatile memory (like a Flash chip or EEPROM). When the system powers up, a small controller or the FPGA itself reads the bitstream from external memory and loads it into the FPGA's internal configuration SRAM cells.
   • Configuration can also often be done interactively using a debugger/programmer cable (like a JTAG cable) connected to a computer running the vendor's software.

Configuration Memory Technologies

The method by which an FPGA stores its configuration is a key differentiator:

• SRAM-Based: The configuration is stored in static RAM cells within the FPGA. This is the most common technology today (used by Xilinx/AMD, Intel/Altera, Lattice, Achronix, GOWIN).

  • Pros: Infinitely reprogrammable, generally uses standard CMOS processes, relatively fast configuration.
  • Cons: Volatile – loses its configuration when power is removed. Requires an external non-volatile memory and a boot sequence to load the bitstream on power-up. Susceptible to single-event upsets (SEUs) in radiation-prone environments (like space), though mitigation techniques exist.

• Flash-Based: The configuration is stored in non-volatile Flash memory cells integrated onto the FPGA die (used by Microchip/Actel, Lattice, GOWIN).

  • Pros: Non-volatile – configuration is retained when power is off ("instant-on"). Does not require external boot memory (though it might be used for larger designs). More resistant to SEUs than SRAM.
  • Cons: Finite number of erase/program cycles (though typically very high). May have slower configuration times than SRAM.

• Antifuse-Based: The configuration is determined by creating permanent, low-resistance connections (fuses) using a high-voltage programming step. Once programmed, the connections are fixed.

  • Pros: Non-volatile, truly "instant-on." Highly tamper-resistant (cannot be easily reprogrammed or reverse-engineered). Extremely radiation tolerant (used in space).
  • Cons: One-Time Programmable (OTP) – cannot be reprogrammed. If there's a bug, you need a new chip. More complex programming process. (Used by Microchip/Actel for specific high-reliability/security applications).

• Obsolete Technologies: Fuse (Bipolar, OTP), PROM (OTP due to packaging), EPROM (UV erasable).

FPGAs vs. ASICs vs. CPLDs

Understanding the landscape of digital chips helps position FPGAs:

• Application-Specific Integrated Circuit (ASIC): A chip designed and manufactured for a single, specific purpose.

  • Pros (compared to FPGA): Much higher performance (speed), lower power consumption, smaller die size (lower unit cost in high volume).
  • Cons (compared to FPGA): Very high upfront Non-Recurring Engineering (NRE) costs (design, masks, fabrication), very long development time, cannot be modified after fabrication.
  • Context: If you were to mass-produce your "computer from scratch," you'd eventually turn the validated FPGA design into an ASIC for cost and performance benefits. FPGAs are often used to prototype ASIC designs.

• Complex Programmable Logic Device (CPLD): An older, simpler type of PLD.

  • Pros (compared to FPGA): Simpler architecture (often based on programmable sum-of-products arrays and macrocells), very predictable timing, often non-volatile (instant-on), lower cost for small amounts of logic.
  • Cons (compared to FPGA): Much lower logic capacity, less flexible interconnect, limited number of registers, generally no complex hard blocks (DSP, processors).
  • Context: CPLDs are often used for smaller "glue logic" tasks, connecting different components on a board, or for the boot sequence logic that might configure an FPGA. For the complexity of building a computer's core logic, FPGAs are far more suitable due to their capacity.

FPGAs sit in a sweet spot, offering high capacity and flexibility with lower NRE and faster time-to-market compared to ASICs, though at a higher unit cost, lower speed, and higher power consumption than an equivalent ASIC. They offer significantly more capacity and flexibility than CPLDs.

Why FPGAs Are Powerful for Complex Tasks (Beyond Basic Logic)

While fundamental logic implementation is the core, FPGAs excel in areas where their unique characteristics shine:

• Parallel Processing: Unlike a CPU that primarily executes instructions sequentially, an FPGA can implement massively parallel architectures. You can instantiate hundreds or thousands of identical or different logic blocks that operate simultaneously. This makes them ideal for tasks like digital signal processing, image processing, data compression, and acceleration of algorithms (like those used in AI/Machine Learning or database searches).
• Custom Hardware Acceleration: You can design specific hardware circuits tailored precisely to accelerate a bottleneck in an algorithm. Instead of running a complex function on a general-purpose CPU, you build dedicated hardware logic for it on the FPGA.
• Reconfigurable Computing: The ability to reprogram FPGAs even during runtime allows for dynamic reconfiguration, where the hardware changes its function based on the current task.

Security Considerations

While flexibility is a strength, it also introduces unique security aspects for FPGAs:

• Bitstream Security: For SRAM-based FPGAs, the configuration bitstream needs to be loaded on power-up, often from external memory. If this bitstream is not encrypted or authenticated, it could potentially be intercepted, copied (design theft), or modified maliciously.
  • Solutions: Modern FPGAs offer robust features like AES encryption of the bitstream and authentication mechanisms to prevent unauthorized loading.
• Tamper Resistance: For high-security applications, one-time programmable (OTP) antifuse FPGAs offer strong physical tamper resistance, as their configuration is permanently "burned" into the silicon.
• Vulnerabilities: Like any complex chip, FPGAs can have vulnerabilities. Historical examples include backdoors found in specific product lines or vulnerabilities allowing bypass of bitstream encryption. This highlights the importance of using vendor-recommended security practices and being aware of potential chip-specific issues.

Conclusion: FPGAs as Your Digital Workbench

For anyone delving into "The Lost Art of Building a Computer from Scratch," FPGAs are indispensable. They provide the hands-on capability to design, build, test, and iterate on digital circuits ranging from simple logic gates to complex computer architectures and custom peripherals. They allow you to understand the physical reality of hardware implementation, the power of parallelism, and the intricacies of turning a logical design into a working electronic circuit, all without the significant barriers of traditional chip fabrication. Mastering FPGA design provides a deep understanding of how the hardware foundation of computing truly works.